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| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||| real - time clock m odule (i 2 c bus) 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 1 pt7c43 11 features ? s upport i 2 c - bus (high speed mode 400khz) ? includes time (h our /m inute /s econd ) and calendar ( century/ y ear /m onth /d ate /d ay ) counter functions ? year 2000 compliant ? automatic switch - over and de select circuitry ? time keeping voltage : 1.2 v to 5.5v ? software clock calibration ? 56 bytes of general purpose ram ? ultra - low battery supply current of 0.3 ? a ? low operating current of 7 0 ? a ? battery or super cap back - up ? operating temperature: - 40 c to 85 c ? automatic leap year compensation ? special software programmable output description the pt7c43 11 serial real - time clock is a low - power clock/calendar w ith a programmable square - wave output. address and data are transferred serially via a 2 - wire bidirectional bu s. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for l eap year. the clock operates in the 24 - hour format indicator. table 1 shows the basic functions of pt7c43 11 . more details are shown in section: overview of functions. pin configuratio n pin description pin no. pin type description 1 x1 i oscillator circuit input. together with x1, 32.768khz crystal is connected between them. or external clock input. 2 x2 o oscillator circuit output. together with x1, 32.768khz crystal is connecte d between them. 3 v bat p battery supply voltage. when v cc >v so 1 , vcc will power the ic. while v cc ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 3 pt7c43 11 real - time clock module (i 2 c bus) maximum ratings storage temperature ................................ ................................ ................................ ............... - 5 5 o c to +1 25 o c ambient temperature with power applied ................................ ................................ ...... - 40 o c to +85 o c supply voltage to ground potential (vcc to gnd) ................................ ...................... - 0.3v to + 7.0 v dc input (all other inputs except vcc & gnd) ................................ ........................... - 0.3v to + 7.0 v dc output voltage ................................ ................................ ................................ ................. - 0.3v to + 7.0 v power dissipatio n ................................ ................................ ................................ .................... 250 mw output current ................................ ................................ ................................ .......................... 20 m a note: stress es greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section s of this spec ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions symbol description min type max unit v cc timing data and ram data maintaining voltage 1.2 - 5.5 v t iming data writing voltage 1.5 - 5.5 timing data reading voltage 1.5 - 5.5 ram data writing voltage 3.0 - 5.5 ram data reading voltage 1.5 - 5.5 v ih input high level 0.7 v cc - v cc +0.3 v il input low level - 0.3 - 0.3 v cc t a operating temperatu re - 40 - 85 oc ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 4 pt7c43 11 real - time clock module (i 2 c bus) dc electrical characteristics ( unless otherwise specified, v cc = 1.5 ~ 5.5 v, t a = - 40 c to +85 c. ) sym. description pin condition min typ max unit v cc timing data and ram data maintaining voltage v cc - 1.2 - 5.5 v timing data writing voltage v cc - 1.5 - 5.5 timing data reading voltage v cc - 1.5 - 5.5 ram data writing voltage v cc - 3.0 - 5.5 ram data reading voltage v cc 1.5 - 5.5 v bat 1 supply voltage v bat - 2.0 3 3 .5 6 v v so 2 battery back - up switchover voltage 3,4 - - v bat - 0. 80 v bat - 0. 50 v bat - 0. 30 5 v i cc current consumption v cc switch freq. = 4 00khz - 70 15 0 ? st standby current v cc sda, scl = v cc C ? bat current consumption v bat osc on, v cc = 0v, v bat = 3v, t a =25 c - 30 0 800 na v il low - level input voltage - - - 0.3 - 0.3v cc v v ih high - level input voltage - - 0.7v cc - v cc +0.5 v o l low - level output voltage sda i ol = 3ma - - 0.4 v pull - up supply voltage (open drain) ft / out - - - 5.5 i il input leakage current scl 0 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 6 pt7c43 11 real - time clock module (i 2 c bus) recommended layout for crystal built - in capacitors specifications and recommended external capacitors parameter symbol typ unit build - in capacitors x1 to gnd c g 18 pf x2 to gnd c d 18 pf recommended external capacitors x1 to gnd c 1 8 pf x2 to gnd c 2 8 pf note : the frequency of crystal can be optimized by external capacitor c 1 and c 2 , for frequency=32.768hz, c 1 and c 2 should meet the equation as below : cpar + [(c 1 +c g )*(c 2 +c d )]/ [(c 1 +c g )+(c 2 +c d )] =c l cpar is all parasitical capacitor between x1 and x2. c l is crystal s load capacitance. crystal specifications parameter symbol min typ max unit nominal frequency f o - 32.768 - khz series resistance esr - - 70 k ? l - 12.5 - pf note : the crystal, traces and crystal input pins should be isolated from rf generating signals. ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 7 pt7c43 11 real - time clock module (i 2 c bus) function description overview of functions 1. clock function cpu can read or write data including the year (last two digits), month, date, day, hour, minute, and second. any (two - digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100 . 2. interface with cpu 2 - wire i 2 c interface. the pt7c4311 continually monitors v cc for an out of tolerance condition. should v cc fall below v so , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. when v cc falls below v so , the device automatically switches from battery to v cc at v so and recognizes inputs. 3. oscillator enable/disable os cillator and time count chain can be enabled or disabled at the same time by st bit . 4. calibration function with the calibration bits properly set, accuracy pt7c43 11 can be improved to better than 2 ppm at 25c. registers 1. allocation of registers addr. (h ex) *1 function register definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 seconds (00 - 59) st *2 s40 s20 s10 s8 s4 s2 s1 01 minutes (00 - 59) ? m40 m20 m10 m8 m4 m2 m1 02 hours (00 - 23) ceb * 3 cb * 3 h20 h10 h8 h4 h2 h1 03 days of the week (0 1 - 07) ? ? ? ? ? w4 w2 w1 04 dates (01 - 31) ? ? d20 d10 d8 d4 d2 d1 05 months (01 - 12) ? ? ? * 8 mo10 mo8 mo4 mo2 mo1 06 years (00 - 99) y80 y40 y20 y10 y8 y4 y2 y1 07 control * 8 out *4 ft * 5 s * 6 calibration * 7 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 8 pt7c43 11 real - time clock module (i 2 c bus) 08~3f ram caution points: *1. pt7c43 11 uses 6 bits for address. that is if write data to 41 h, the data will be written to 0 1 h address register. *2. stop bit. when this bit is set to 1, oscillator and time count chain are both stopped. *3. ceb: century enable bit. cb: century bit. *4. cont rol ft /out pin output dc level when 512hz square wave is disabled. *5. frequency test. 512hz s quare wave output is enable d at ft /out pin , which is using for frequency test. * 6 . sign bit. 1 indicates positive calibration ; 0 indicates negative calibra tion . * 7 . using for modifying count frequen cy. if 20ppm is wanted to slow down the count frequen cy, 10 (01010) should be loaded. * 8 . i nitialize the control and status register to 10000000 if calibration function is not required . 2. control and status r egister addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 07 control out ft s calibration (default) 1 0 1 undefined undefined undefined undefined undefined a) out ? out : set pin 7 output dc level. . out data description read / write 1 set high level at pin 7 . default 0 set low level at pin 7. b) 512hz output ? ft : 512hz square wave output enable bit, using for frequency test. ft data description read / write 0 disable 512hz output at pin 7. default 1 enable 512hz output at pin 7. c) calibration bits ? s : sign bi t. s data description read / write 1 indicate positive calibration. default 0 indicate negative calibration. calibration: calibration occurs within a 64minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either short ened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore , each calibratio n step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or C 2.034 ppm of adjustment per calibration step in the calibration register. assuming that the oscillator is in fact ru nning at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or C 5.35 seconds per month which corresponds to a total range of +5.5 or C 2.75 minutes per month. for example, a reading of 512.01024hz would indicate a +20 ppm oscillator frequency error, requiring a C 10 (xx001010) to be loaded into the calibration byte for correction. ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 9 pt7c43 11 real - time clock module (i 2 c bus) clock calibration 3. time counter time digit display (in bcd code): ? second digits: range from 00 to 59 and carried to minute digits when increme nted from 59 to 00. ? minute digits: range from 00 to 59 and carried to hour digits when incremented from 59 to 00. ? hour digits: see description on the /12, 24 bit. carried to day and day - of - the - week digits when incremented from 11 p.m. to 12 a.m. or 23 to 0 0. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 00 seconds st s40 s20 s10 s8 s4 s2 s1 (default) 0 undefined undefined undefined undefined undefined undefined undefined 01 minutes ? *2 m40 m20 m10 m8 m4 m2 m1 (default) 0 undefined undefined undefin ed undefined undefined undefined undefined 02 hours ceb * 3 cb * 3 h20 h10 h8 h4 h2 h1 (default) 1 1 undefined undefined undefined undefined undefined undefined * note 1 : st bit: stop oscillation and time count chain. * note 2 : do not care. * note 3 : centu ry enable bit and century bit. 4. days of the week counter the day counter is a divide - by - 7 counter that counts from 01 to 07 and up 07 before starting again from 01. values that correspond to the day of week are user defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illogical time and date entries result in undefined operation. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 03 day s of the week ? ? ? ? ? 5. calendar counter the data format is bcd format. ? day digits: range from 1 to 31 (for january, march, may, july, august, october and december). range from 1 to 30 (for april, june, september and november ). range f rom 1 to 29 (for february in leap years). range from 1 to 28 (for february in ordinary years). carried to month digit s when cycled to 1. ? month digits: range from 1 to 12 and carried to year digits when cycled to 1. ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 10 pt7c43 11 real - time clock module (i 2 c bus) ? year digits: range from 00 to 99 and 00, 04, 08, , 92 and 96 are counted as leap years. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 04 dates (01 - 31) ? ? ? ? ? communi cation 1. i 2 c bus interface a) overview of i 2 c - bus the i 2 c bus supports bi - directional communications via two signal lines: the sda (data) line and scl (clock) line. a combination of these two signals is used to transmit and receive communication start/stop si gnals, data signals, acknowledge signals, and so on. both the scl and sda signals are held at high level whenever communications are not being performed. the starting and stopping of communications is controlled at the rising edge or falling edge of sda wh ile scl is at high level. during data transfers, data changes that occur on the sda line are performed while the scl line is at low level, and on the receiving sid e the data is captured while the scl line is at high level. in either case, the data is trans ferred via the scl line at a rate of one bit per clock pulse. the i 2 c bus device does not include a chip select pin such as is found in ordinary logic devices. instead of using a chip select pin, slave addresses are allocated to each device and the receivi ng device responds to communications only when its slave address matches the slave address in the received data. b) system configuration all ports connected to the i 2 c bus must be either open drain or open collector ports in order to enable and connections t o multiple devices. scl and sda are both connected to the vdd line via a pull - up resistance. consequently, scl and sda are both held at high level when the bus is released (when communication is not being performed). f ig. 1 system configuration master mcu slave rtc other peripheral device v cc sda scl note: when there is only one master, the mcu is ready for driving scl to "h" and r p of scl may not required. r p r p ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 11 pt7c43 11 real - time clock module (i 2 c bus) c) starting and stopping i 2 c bus commu nications start condition, repeated start condition, and stop condition ? start condition sda level changes from high to low while scl is at high level ? stop condition sda level changes from low to high while scl is at high level ? repeated star t condition (restart condition) in some cases, the start condition occurs between a previous start condition and the next stop condition, in which case the second start condition is distinguished as a restart condition. since the required status is the sam e as for the start condition, the sda level changes from high to low while scl is at high level. d) data transfers and acknowledge responses during i 2 c - bus communication ? data transfers data transfers are performed in 8 - bit (1 byte) units once the start condi tion has occurred. there is no limit on the amount (bytes) of data that are transferred between the start condition and stop condition. the address auto increment function operates during both write and read operations. updating of data on the transmitt er (transmitting side)'s sda line is performed while the scl line is at low level. the receiver (receiving side) captures data while the scl line is at high level. *note : with caution that if the sda data is changed while the scl line is at hi gh level, it will be treated as a start, restart, or stop condition. fig . 2 starting and stopping on i 2 c bus ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 12 pt7c43 11 real - time clock module (i 2 c bus) ? data acknowledge response (ack signal) when transferring data, the receiver generates a confirmation response (ack signal, low active) each time an 8 - bit data segment is received. if th ere is no ack signal from the receiver, it indicates that normal communication has not been established. (this does not include instances where the master device intentionally does not generate an ack signal.) immediately after the falling edge of the cl ock pulse corresponding to the 8th bit of data on the scl line, the transmitter releases the sda line and the receiver sets the sda line to low (= acknowledge) level. after transmitting the ack signal, if the master remains the receiver for t ransfer of the next byte, the sda is released at the falling edge of the clock corresponding to the 9th bit of data on the scl line. data transfer resumes when the master becomes the transmitter. when the master is the receiver, if the master does not sen d an ack signal in response to the last byte sent from the slave, that indicates to the transmitter that data transfer has ended. at that point, the transmitter continues to release the sda and aw aits a stop condition from the master. e) slave address the i 2 c bus device does not include a chip select pin such as is found in ordinary logic devices. instead of using a chip select pi n, slave addresses are allocated to each device. all communications begin with transmitting the [start condition] + [slave address (+ r/w specification)]. the receiving device responds to this communication only when the specified slave address it has received matches its own slave address. slave addresses have a fixed length of 7 bits. see table for the details. an r/w bit is added to each 7 - bit slave address during 8 - bit transfers. operation transfer data slave address r / w bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read d1 h 1 1 0 1 0 0 0 1 (= read) write d0 h 0 (= write) 2. i 2 c buss basic transfer format scl from master 1 2 8 9 sda from transmitter (sending side) sda from receiver (receiving side) release sda low active ack signal s start indication p stop indication sr restart indication a rtc acknowledge a master acknowledge ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 13 pt7c43 11 real - time clock module (i 2 c bus) a) write via i 2 c bus b) read via i 2 c bus ? standard read ? simplified read note: 1. the above steps are an example of transfers of one or two bytes only. there is no limit to the number of bytes transferred durin g actual communications. 2. 49h, 4ah are used as test mode address. customer should not use the addresses. slave address (7 bits) 1 1 0 1 0 0 0 0 write addr. setting slave address + write specification address specifies the write start address. a bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit a p write data s a a c k a c k a c k start stop slave address (7 bits) 1 1 0 1 0 0 0 0 write slave address + write specification address specifies the read start address. addr. setting a s slave address (7 bits) 1 1 0 1 0 0 0 1 read slave address + read specification data read (1) data is read from the specified start address and address auto increment. a bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit /a p sr 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit bit data read (2) address auto increment to set the address for the next data to be read. a c k n o a c k a a c k a c k a c k a start stop restart data read (2) address register auto increment to set the address for the next data to be read. data read (1) data is read from the address pointed by the internal address register and address auto increment. slave address (7 bits) 1 1 0 1 0 0 0 1 read a bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit /a p s 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit bit a c k n o a c k a c k a stop start slave address + read specification ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 14 pt7c43 11 real - time clock module (i 2 c bus) mechanical information we ( lead free and green 8 - pin soic) min max a 1.350 1.750 a1 0.100 0.250 a2 1.350 1.550 b 0.330 0.510 c 0.170 0.250 d 4.700 5.100 e 3.800 4.000 e1 5.800 6.200 e l 0.400 1.270 0 8 symbol dimensions in millimeters 1.27 bsc note: 1) controlling dimensions in millimeters. 2) ref : jedec ms - 012e/aa ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 15 pt7c43 11 real - time clock module (i 2 c bus) z e e (lead free and green 8 - pin t dfn) symbol min. max a 0.700 0.800 a1 0.000 0.500 a3 d 1.924 2.076 e 2.924 3.076 d1 1.400 1.600 e1 1.400 1.600 k b 0.200 0.300 e l 0.224 0.376 pkg. dimensions(mm) 0.203ref 0.200min 0.500typ note: ref: jedec mo-229 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2015 - 0 6 - 000 2 pt0 3 22 - 8 0 6 / 1 6 /1 5 16 pt7c43 11 real - time clock module (i 2 c bus) ordering information part number package code package pt7c4311w e w lead f ree and green 8 - pin soic ( w ) pt7c4311wex w lead free and green 8 - pin soic (w) tape/reel pt7c4311ze e ze lead free and green 8 - pin tdfn ( ze ) pt7c4311ze ex ze le ad free and green 8 - pin tdfn ( ze ) tape/reel notes: ? e = pb - free and green ? adding x suffix = tape /r eel pericom semiconductor corporation ? 1 - 800 - 435 - 2336 ? www.pericom.com pericom reserves the right to make changes t o its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. pericom does not assume any responsibility for use of any circuitry described other than the circu itry embodied in pericom product. the company makes no representations that circuitry described herein is free from patent infringement or other rights, of pericom |
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